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VLSID
2002
IEEE
125views VLSI» more  VLSID 2002»
14 years 10 months ago
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors
This paper shows that software pipelining can be an effective technique for code generation for coarse-grained reconfigurable instruction set processors. The paper describes a tec...
Francisco Barat, Murali Jayapala, Pieter Op de Bee...
RTAS
2008
IEEE
14 years 4 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
LCTRTS
2007
Springer
14 years 4 months ago
Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration o
Industry’s demand for flexible embedded solutions providing high performance and short time-to-market has led to the development of configurable and extensible processors. The...
Richard Vincent Bennett, Alastair Colin Murray, Bj...
CAL
2005
13 years 9 months ago
On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor
Previous research on runahead execution took it for granted as a prefetch-only technique. Even though the results of instructions independent of an L2 miss are correctly computed d...
Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt
TSP
2008
123views more  TSP 2008»
13 years 9 months ago
A Rough Programming Approach to Power-Balanced Instruction Scheduling for VLIW Digital Signal Processors
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
Shu Xiao, Edmund Ming-Kit Lai