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DATE
2009
IEEE
189views Hardware» more  DATE 2009»
14 years 4 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
MICRO
1996
IEEE
81views Hardware» more  MICRO 1996»
14 years 2 months ago
Instruction Scheduling and Executable Editing
Modern microprocessors offer more instruction-level parallelism than most programs and compilers can currently exploit. The resulting disparity between a machine's peak and a...
Eric Schnarr, James R. Larus
MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
13 years 7 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
ISCA
1989
IEEE
109views Hardware» more  ISCA 1989»
14 years 1 months ago
Improving Performance of Small On-Chip Instruction Caches
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
Matthew K. Farrens, Andrew R. Pleszkun
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
14 years 2 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith