Sciweavers

1563 search results - page 52 / 313
» Flexible instruction processors
Sort
View
FPL
2006
Springer
105views Hardware» more  FPL 2006»
14 years 1 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...
WCAE
2006
ACM
14 years 3 months ago
PSATSim: an interactive graphical superscalar architecture simulator for power and performance analysis
Two of the most important design issues for modern processors are power and performance. It is important for students in computer organization classes to understand the tradeoff b...
Clint W. Smullen, Tarek M. Taha
VLSID
1999
IEEE
122views VLSI» more  VLSID 1999»
14 years 2 months ago
Formal Verification of an ARM Processor
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
Vishnu A. Patankar, Alok Jain, Randal E. Bryant
ASPLOS
1992
ACM
14 years 2 months ago
Efficient Superscalar Performance Through Boosting
The foremost goal of superscalar processor design is to increase performance through the exploitation of instruction-level parallelism (ILP). Previous studies have shown that spec...
Michael D. Smith, Mark Horowitz, Monica S. Lam
HPCA
2006
IEEE
14 years 10 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...