1563 search results - page 54 / 313 » Flexible instruction processors |
ISCA
2003
IEEE
14 years 3 months ago
2003
IEEE
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
HPCA
1995
IEEE
14 years 1 months ago
1995
IEEE
The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...
PDPTA
2000
13 years 11 months ago
2000
Abstract In this paper, we propose a microprocessor architecture which eciently utilizes nextgeneration semiconductor technology. While the technology makes it possible to integrat...
CONCURRENCY
2006
13 years 10 months ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
MICRO
1998
IEEE
14 years 2 months ago
1998
IEEE
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...