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DSN
2007
IEEE
14 years 4 months ago
Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance
A new approach is proposed that exploits repetition inherent in programs to provide low-overhead transient fault protection in a processor. Programs repeatedly execute the same in...
Vimal K. Reddy, Eric Rotenberg
DATE
2008
IEEE
117views Hardware» more  DATE 2008»
14 years 4 months ago
CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches
Cache-Content-Duplication (CCD) occurs when there is a miss for a block in a cache and the entire content of the missed block is already in the cache in a block with a different t...
Marios Kleanthous, Yiannakis Sazeides
DAC
1996
ACM
14 years 2 months ago
Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures
The advent of parallel executing Address Calculation Units (ACUs) in Digital Signal Processor (DSP) and Application Specific InstructionSet Processor (ASIP) architectures has made...
Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerra...
VLSID
2007
IEEE
97views VLSI» more  VLSID 2007»
14 years 10 months ago
Efficient Microprocessor Verification using Antecedent Conditioned Slicing
We present a technique for automatic verification of pipelined microprocessors using model checking. Antecedent conditioned slicing is an efficient abstraction technique for hardw...
Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraha...
IPPS
2005
IEEE
14 years 3 months ago
Control-Flow Independence Reuse via Dynamic Vectorization
Current processors exploit out-of-order execution and branch prediction to improve instruction level parallelism. When a branch prediction is wrong, processors flush the pipeline ...
Alex Pajuelo, Antonio González, Mateo Valer...