1563 search results - page 60 / 313 » Flexible instruction processors |
ISLPED
1999
ACM
14 years 2 months ago
1999
ACM
We propose a technique for reducing the energy required by rmware code to execute on embedded systems. The method is based on the idea of compressing the most commonly executed in...
TVLSI
2002
13 years 9 months ago
2002
We propose a technique for reducing the energy spent in the memory-processor interface of an embedded system during the execution of firmware code. The method is based on the idea ...
ISSS
1996
IEEE
14 years 2 months ago
1996
IEEE
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into four parts. First, we propose a branch instructio...
DAC
2009
ACM
13 years 11 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
MICRO
1992
IEEE
14 years 2 months ago
1992
IEEE
This paper describes a single chip Multiple Instruction Stream Computer (MISC) capable of extracting instruction level parallelism from a broad spectrum of programs. The MISC arch...