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PPOPP
1990
ACM
14 years 2 months ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
IEEEPACT
2002
IEEE
14 years 2 months ago
Effective Compilation Support for Variable Instruction Set Architecture
Traditional compilers perform their code generation tasks based on a fixed, pre-determined instruction set. This paper describes the implementation of a compiler that determines ...
Jack Liu, Timothy Kong, Fred C. Chow
CASES
2001
ACM
14 years 1 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
ISCAPDCS
2007
13 years 11 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
TC
1998
13 years 9 months ago
Cipher Instruction Search Attack on the Bus-Encryption Security Microcontroller DS5002FP
Abstract—A widely used bus-encryption microprocessor is vulnerable to a new practical attack. This type of processor decrypts onthe-fly while fetching code and data, which are st...
Markus G. Kuhn