Sciweavers

1563 search results - page 69 / 313
» Flexible instruction processors
Sort
View
ISCAS
2008
IEEE
173views Hardware» more  ISCAS 2008»
14 years 4 months ago
Analysis of video filtering on the cell processor
— In this paper an analysis of bi-dimensional video filtering on the Cell Broadband Engine Processor is presented. To evaluate the processor, a highly adaptive filtering algori...
Arnaldo Azevedo, Cor Meenderinck, Ben H. H. Juurli...
JCP
2008
216views more  JCP 2008»
13 years 10 months ago
Design Overview Of Processor Based Implantable Pacemaker
Implantable pacemaker is a battery operated real time embedded system, which includes software/hardware codesign strategy. As it is placed within the heart by surgery, battery life...
Santosh D. Chede, Kishore D. Kulat
JCIT
2007
63views more  JCIT 2007»
13 years 10 months ago
Optimizing Reaching Definitions Overhead in Queue Processors
Queue computers are a viable option for embedded systems design. Queue computers feature a dense instruction set, high parallelism, low hardware complexity. In this paper we propo...
Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderaze...
ICCD
2000
IEEE
96views Hardware» more  ICCD 2000»
14 years 2 months ago
AMULET3: A 100 MIPS Asynchronous Embedded Processor
AMULET3 is a 32-bit asynchronous processor core that is fully instruction set compatible with the clocked ARM cores. It represents the culmination of ten years of research and dev...
Stephen B. Furber, David A. Edwards, Jim D. Garsid...
ICCD
2002
IEEE
228views Hardware» more  ICCD 2002»
14 years 6 months ago
JMA: The Java-Multithreading Architecture for Embedded Processors
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
Panit Watcharawitch, Simon W. Moore