43 search results - page 4 / 9 » Floorplan area minimization using Lagrangian relaxation |
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
ISPD
2005
ACM
14 years 1 months ago
2005
ACM
In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and the bus specification (the width of each bus and the blocks that the bus need to g...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice o...
ASPDAC
2000
ACM
13 years 12 months ago
2000
ACM
Simulated annealing has been one of the most popular stochastic optimization methods used in the VLSI CAD field in the past two decades for handling NP-hard optimization problems...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...