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ITC
2003
IEEE
214views Hardware» more  ITC 2003»
14 years 18 days ago
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume
This paper presents an approach for reducing the test data volume that has to be stored in ATE vector memory for IC manufacturing testing. We exploit the capabilities of present A...
Harald P. E. Vranken, Friedrich Hapke, Soenke Rogg...
TCAD
2002
73views more  TCAD 2002»
13 years 7 months ago
A timing-constrained simultaneous global routing algorithm
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar
DAC
2009
ACM
14 years 8 months ago
Multicore parallel min-cost flow algorithm for CAD applications
Computational complexity has been the primary challenge of many VLSI CAD applications. The emerging multicore and manycore microprocessors have the potential to offer scalable perf...
Yinghai Lu, Hai Zhou, Li Shang, Xuan Zeng
DATE
2009
IEEE
118views Hardware» more  DATE 2009»
14 years 2 months ago
Gate sizing for large cell-based designs
—Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices...
Stephan Held
ICC
2007
IEEE
116views Communications» more  ICC 2007»
14 years 1 months ago
Fast Handover Scheme for Real-Time Applications in Mobile WiMAX
—Mobile WiMAX is one of the most promising technologies for broadband wireless communication. The IEEE 802.16e standard for Mobile WiMAX, the enhanced version of the IEEE 802.16 ...
Wenhua Jiao, Pin Jiang, Yuanyuan Ma