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» Flow Grammars - a Flow Analysis Methodology
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IPPS
2007
IEEE
14 years 1 months ago
Pipelining Tradeoffs of Massively Parallel SuperCISC Hardware Functions
Parallel processing using multiple processors is a well-established technique to accelerate many different classes of applications. However, as the density of chips increases, ano...
Colin J. Ihrig, Justin Stander, Alex K. Jones
APVIS
2001
13 years 9 months ago
Visual Mapping of Articulable Tacit Knowledge
Tacit knowledge has long been recognised, however its research has focused largely on who is more likely to have this store of knowledge, rather than taking this one step further ...
Peter Busch, Debbie Richards, Christopher N. G. Da...
IPPS
1999
IEEE
13 years 11 months ago
Tailor-Made Operating Systems for Embedded Parallel Applications
This paper presents the Pure/Epos approach to deal with the high complexity of adaptable operating systems and also to diminish the distance between application and operating syste...
Antônio Augusto Fröhlich, Wolfgang Schr...
DSD
2010
IEEE
221views Hardware» more  DSD 2010»
13 years 5 months ago
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jea...
ASPDAC
2010
ACM
112views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Optimizing blocks in an SoC using symbolic code-statement reachability analysis
Abstract-- Optimizing blocks in a System-on-Chip (SoC) circuit is becoming more and more important nowadays due to the use of third-party Intellectual Properties (IPs) and reused d...
Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo