444 search results - page 27 / 89 » Flow Level Simulation of Large IP Networks |
ISQED
2008
IEEE
14 years 2 months ago
2008
IEEE
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
TON
2008
13 years 7 months ago
2008
By allowing end hosts to make independent routing decisions at the application level, different overlay networks may unintentionally interfere with each other. This paper describes...
ANCS
2006
ACM
14 years 1 months ago
2006
ACM
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
AINA
2003
IEEE
13 years 11 months ago
2003
IEEE
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...
DATE
2010
IEEE
13 years 12 months ago
2010
IEEE
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...