444 search results - page 49 / 89 » Flow Level Simulation of Large IP Networks |
QEST
2007
IEEE
14 years 1 months ago
2007
IEEE
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
PDP
2008
IEEE
14 years 2 months ago
2008
IEEE
The scalability properties of DHT based overlay networks is considered satisfactory. However, in large scale systems this might still cause a problem since they have a logarithmic...
HPCA
2000
IEEE
14 years 9 hour ago
2000
IEEE
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...