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DATE
2008
IEEE
145views Hardware» more  DATE 2008»
14 years 3 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
SAMOS
2007
Springer
14 years 3 months ago
An Evolutionary Approach to Area-Time Optimization of FPGA designs
—This paper presents a new methodology based on evolutionary multi-objective optimization (EMO) to synthesize multiple complex modules on programmable devices (FPGAs). It starts ...
Fabrizio Ferrandi, Pier Luca Lanzi, Gianluca Paler...
STACS
2007
Springer
14 years 3 months ago
New Approximation Algorithms for Minimum Cycle Bases of Graphs
We consider the problem of computing an approximate minimum cycle basis of an undirected non-negative edge-weighted graph G with m edges and n vertices; the extension to directed ...
Telikepalli Kavitha, Kurt Mehlhorn, Dimitrios Mich...
UML
2005
Springer
14 years 2 months ago
Using Process Algebra to Validate Behavioral Aspects of Object-Oriented Models
We present in this paper a rigorous and automated based approach for the behavioral validation of control software systems. This approach relies on metamodeling, model-transformati...
Alban Rasse, Jean-Marc Perronne, Pierre-Alain Mull...
CASES
2004
ACM
14 years 2 months ago
Balancing design options with Sherpa
Application specific processors offer the potential of rapidly designed logic specifically constructed to meet the performance and area demands of the task at hand. Recently, t...
Timothy Sherwood, Mark Oskin, Brad Calder