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DATE
2006
IEEE
117views Hardware» more  DATE 2006»
14 years 23 days ago
Formal verification of systemc designs using a petri-net based representation
This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is ...
Daniel Karlsson, Petru Eles, Zebo Peng
IFIPTCS
2000
13 years 10 months ago
Masaccio: A Formal Model for Embedded Components
Masaccio is a formal model for hybrid dynamical systems which are built from atomic discrete components (di erence equations) and atomic continuous components (di erential equation...
Thomas A. Henzinger
HASE
1999
IEEE
13 years 11 months ago
Model Checking UML Statechart Diagrams Using JACK
Statechart Diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modeling Language (UML). In this paper we present a branchin...
Stefania Gnesi, Diego Latella, Mieke Massink
DATE
2004
IEEE
130views Hardware» more  DATE 2004»
13 years 10 months ago
Utilizing Formal Assertions for System Design of Network Processors
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Fe...
ACSD
2009
IEEE
136views Hardware» more  ACSD 2009»
14 years 1 months ago
Model Checking Verilog Descriptions of Cell Libraries
We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symb...
Matthias Raffelsieper, Jan-Willem Roorda, Mohammad...