Sciweavers

575 search results - page 34 / 115
» Formal Coverification of Embedded Systems Using Model Checki...
Sort
View
ISOLA
2010
Springer
13 years 5 months ago
Model-Driven Design-Space Exploration for Embedded Systems: The Octopus Toolset
Abstract. The complexity of today's embedded systems and their development trajectories requires a systematic, model-driven design approach, supported by tooling wherever poss...
Twan Basten, Emiel van Benthum, Marc Geilen, Marti...
FMICS
2009
Springer
14 years 1 months ago
Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models
Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve nondeterminism, which in turn, poses a challenge to th...
Matthias Raffelsieper, Mohammad Reza Mousavi, Jan-...
ATVA
2007
Springer
134views Hardware» more  ATVA 2007»
13 years 11 months ago
Formal Modeling and Verification of High-Availability Protocol for Network Security Appliances
One of the prerequisites for information society is secure and reliable communication among computing systems. Accordingly, network security appliances become key components of inf...
Moonzoo Kim
CL
2008
Springer
13 years 7 months ago
Automatic synthesis and verification of real-time embedded software for mobile and ubiquitous systems
Currently available application frameworks that target the automatic design of real-time embedded software are poor in integrating functional and non-functional requirements for m...
Pao-Ann Hsiung, Shang-Wei Lin
DAC
1996
ACM
13 years 11 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson