531 search results - page 4 / 107 » Formal Methods for Networks on Chips |
148
Voted
DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
This paper presents a novel architecture for on-chip neural network training using particle swarm optimization (PSO). PSO is an evolutionary optimization algorithm with a growing ...
148
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NCA
2008
IEEE
15 years 10 months ago
2008
IEEE
In this paper we consider the frameworks of Process Algebra and I/O Automata and we apply both towards the verification of a distributed leader-election protocol. Based on the tw...
114
Voted
ISQED
2006
IEEE
15 years 9 months ago
2006
IEEE
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
86
Voted
ICIP
1994
IEEE
16 years 5 months ago
1994
IEEE
A newmethodfornormalizingandquantizingimagesispresented. The method is based oncalculating a local referenceframeforthe imagegray levels. "helevels of the referenceframeareca...
124
Voted
UML
2004
Springer
15 years 8 months ago
2004
Springer
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...