478 search results - page 29 / 96 » Formal Methods for Specifying, Validating, and Verifying Req... |
IJCM
2002
13 years 8 months ago
2002
Abstract. The class of systems of uniform recurrence equations (UREs) is closed under unimodular transformations. As a result, every systolic array described by a unimodular mappin...
FDL
2007
IEEE
14 years 3 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
EMSOFT
2007
Springer
14 years 20 days ago
2007
Springer
The soundness of device drivers generally cannot be verified in isolation, but has to take into account the reactions of the hardware devices. In critical embedded systems, interf...
AAMAS
1999
Springer
13 years 8 months ago
1999
Springer
Interaction protocols are specific, often standard, constraints on the behaviors of autonomous agents in a multiagent system. Protocols are essential to the functioning of open sys...
IFM
2004
Springer
14 years 2 months ago
2004
Springer
Recent work on combining CSP and B has provided ways of describing systems comprised of components described in both B (to express requirements on state) and CSP (to express intera...