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» Formal Modeling of Process Migration
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EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
13 years 12 months ago
A process algebra interpretation of a verification oriented overlanguage of VHDL
The VOVHDL language was defined as a verification oriented VHDL
Catherine Bayol, Bernard Soulas, Dominique Borrion...
CAISE
2005
Springer
14 years 1 months ago
Development of a formal REA-ontology Representation
Business domain ontologies offer great opportunities for facilitating communication between people in business, for improving the enterprise system engineering processes and for cr...
Frederik Gailly, Geert Poels
HASE
2008
IEEE
14 years 2 months ago
Formal Support for Quantitative Analysis of Residual Risks in Safety-Critical Systems
With the increasing complexity in software and electronics in safety-critical systems new challenges to lower the costs and decrease time-to-market, while preserving high assuranc...
Jonas Elmqvist, Simin Nadjm-Tehrani
ISORC
2000
IEEE
13 years 11 months ago
Verification of UML-Based Real-Time System Designs by Means of cTLA
The Unified Modeling Language UML is well-suited for the design of real-time systems. In particular, the design of dynamic system behaviors is supported by interaction diagrams an...
Günter Graw, Peter Herrmann, Heiko Krumm
EURODAC
1995
IEEE
137views VHDL» more  EURODAC 1995»
13 years 11 months ago
A formal non-heuristic ATPG approach
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...