67 search results - page 6 / 14 » Formal Verification of Digital Circuits Using Symbolic Terna... |
ENTCS
2006
13 years 7 months ago
2006
The application of formal methods to analog and mixed signal circuits requires efficient methods tructing abstractions of circuit behaviors. This paper concerns the verification o...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
CHARME
2001
Springer
13 years 11 months ago
2001
Springer
We consider the formal verification of the cache coherence protocol of the Stanford FLASH multiprocessor for N processors. The proof uses the SMV proof assistant, a proof system ba...
CAV
2009
Springer
13 years 11 months ago
2009
Springer
tic modalities for correctness [16]. The release described in this abstract is a complete rebuild of a preliminary experimental checker [14]. The model input language includes vari...
ARTS
1999
Springer
14 years 20 hour ago
1999
Springer
Model checking can tell us whether a system is correct; probabilistic model checking can also tell us whether a system is timely and reliable. Moreover, probabilistic model checkin...