176 search results - page 13 / 36 » Formal Verification of Gate-Level Computer Systems |
FORMATS
2009
Springer
13 years 11 months ago
2009
Springer
Probabilistic timed automata (PTAs) are used for formal modelling and verification of systems with probabilistic, nondeterministic and real-time behaviour. For non-probabilistic ti...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
ATVA
2006
Springer
13 years 11 months ago
2006
Springer
Of special interest in formal verification are safety properties, which assert that the system always stays within some allowed region. Each safety property can be associated with...
ENTCS
2006
13 years 7 months ago
2006
In this paper, we address the issue of the formal verification of real-time systems in the context of a preemptive scheduling policy. We propose an algorithm which computes the st...
SPIN
2000
Springer
13 years 11 months ago
2000
Springer
We describe a tool, called AX, that can be used in combination with the model checker SPIN to efficiently verify logical properties of distributed software systems implemented in A...