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» Formal Verification of Gate-Level Computer Systems
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ACSC
2004
IEEE
13 years 11 months ago
Java Implementation Verification Using Reverse Engineering
An approach to system verification is described in which design artefacts produced during forward engineering are automatically compared to corresponding artefacts produced during...
David J. A. Cooper, Benjamin Khoo, Brian R. von Ko...
BMCBI
2007
114views more  BMCBI 2007»
13 years 7 months ago
Mining and state-space modeling and verification of sub-networks from large-scale biomolecular networks
Background: Biomolecular networks dynamically respond to stimuli and implement cellular function. Understanding these dynamic changes is the key challenge for cell biologists. As ...
Xiaohua Hu, Fang-Xiang Wu
DAC
2003
ACM
14 years 8 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
VMCAI
2010
Springer
14 years 4 months ago
Advances in Probabilistic Model Checking
In the recent years, there have been a large amount of investigations on safety verification of uncertain continuous systems. In engineering and applied mathematics, this verificat...
Joost-Pieter Katoen
ISOLA
2010
Springer
13 years 5 months ago
Analysing Message Sequence Graph Specifications
We give a detailed construction of a finite-state transition system for a com-connected Message Sequence Graph. Though this result is fairly well-known in the literature there has...
Joy Chakraborty, Deepak D'Souza, K. Narayan Kumar