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» Formal Verification of Gate-Level Computer Systems
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ATVA
2007
Springer
134views Hardware» more  ATVA 2007»
13 years 11 months ago
Formal Modeling and Verification of High-Availability Protocol for Network Security Appliances
One of the prerequisites for information society is secure and reliable communication among computing systems. Accordingly, network security appliances become key components of inf...
Moonzoo Kim
DAC
2006
ACM
14 years 1 months ago
Use of C/C++ models for architecture exploration and verification of DSPs
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
David Brier, Raj S. Mitra
FCSC
2010
170views more  FCSC 2010»
13 years 4 months ago
Formal verification of concurrent programs with read-write locks
Abstract Read-write locking is an important mechanism to improve concurrent granularity, but it is difficult to reason about the safety of concurrent programs with read-write locks...
Ming Fu, Yu Zhang, Yong Li
ECOWS
2006
Springer
13 years 11 months ago
Formal Modelling and Verification of an Asynchronous Extension of SOAP
Current web services are largely based on a synchronous request-response model that uses the Simple Object Access Protocol SOAP. Next-generation telecommunication networks, on the...
Maurice H. ter Beek, Stefania Gnesi, Franco Mazzan...
HVC
2007
Springer
153views Hardware» more  HVC 2007»
13 years 11 months ago
On the Architecture of System Verification Environments
Implementations of computer systems comprise many layers and employ a variety of programming languages. Building such systems requires support of an often complex, accompanying too...
Mark A. Hillebrand, Wolfgang J. Paul