216 search results - page 37 / 44 » Formal Verification of Safety Properties in Timed Circuits |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
This paper presents a power grid analyzer based on a random walk technique. A linear-time algorithm is first demonstrated for DC analysis, and is then extended to perform transien...
EJWCN
2010
13 years 2 months ago
2010
Model checking (MC) is a formal verification technique which has known and still knows a resounding success in the computer science community. Realizing that the distributed power...
WWW
2004
ACM
14 years 8 months ago
2004
ACM
Complex Semantic Web (SW) services may have intricate data state, autonomous process behavior and concurrent interactions. The design of such SW service systems requires precise a...
LICS
1994
IEEE
13 years 11 months ago
1994
IEEE
The modal mu-calculus is an expressive logic that can be used to specify safety and liveness properties of concurrent systems represented as labeled transition systems (LTSs). We ...
CADE
2007
Springer
14 years 7 months ago
2007
Springer
Manna and Pnueli have extensively shown how a mixture of first-order logic (FOL) and discrete Linear time Temporal Logic (LTL) is sufficient to precisely state verification problem...