216 search results - page 38 / 44 » Formal Verification of Safety Properties in Timed Circuits |
GLVLSI
2008
IEEE
13 years 7 months ago
2008
IEEE
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
Embedded systems are often used in safety-critical environments. Thus, thorough testing of them is mandatory. A quite active research area is the automatic test-case generation fo...
FM
2003
Springer
14 years 21 days ago
2003
Springer
We present a novel application on model checking through SPIN as a means for verifying purely descriptive specifications written in TRIO, a first order, linear-time temporal logic ...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
CRYPTO
2010
Springer
13 years 8 months ago
2010
Springer
Homomorphic encryption (HE) schemes enable computing functions on encrypted data, by means of a public Eval procedure that can be applied to ciphertexts. But the evaluated ciphert...