219 search results - page 10 / 44 » Formal Verification of the Ricart-Agrawala Algorithm |
FDL
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
CONCUR
2006
Springer
13 years 11 months ago
2006
Springer
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
FMCAD
2004
Springer
13 years 11 months ago
2004
Springer
The main challenge in BDD-based verification is dealing with the memory explosion problem during reachability analysis. In this paper we advocate a methodology to handle this probl...