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» Formal Verification of the Ricart-Agrawala Algorithm
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PPOPP
2010
ACM
14 years 4 months ago
Featherweight X10: a core calculus for async-finish parallelism
We present a core calculus with two of X10's key constructs for parallelism, namely async and finish. Our calculus forms a convenient basis for type systems and static analys...
Jonathan K. Lee, Jens Palsberg
DAC
2007
ACM
13 years 11 months ago
Memory Modeling in ESL-RTL Equivalence Checking
When designers create RTL models from a system-level specification, arrays in the system-level model are often implemented as memories in the RTL. Knowing the correspondence betwe...
Alfred Kölbl, Jerry R. Burch, Carl Pixley
FMICS
2006
Springer
13 years 11 months ago
Can Saturation Be Parallelised?
Abstract. Symbolic state-space generators are notoriously hard to parallelise. However, the Saturation algorithm implemented in the SMART verification tool differs from other seque...
Jonathan Ezekiel, Gerald Lüttgen, Radu Simini...
DAC
2004
ACM
14 years 8 months ago
Abstraction refinement by controllability and cooperativeness analysis
ion Refinement by Controllability and Cooperativeness Analysis Freddy Y.C. Mang and Pei-Hsin Ho Advanced Technology Group, Synopsys, Inc. {fmang, pho}@synopsys.com nt a new abstrac...
Freddy Y. C. Mang, Pei-Hsin Ho
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
13 years 12 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...