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» Formal analysis of hardware requirements
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DATE
2002
IEEE
102views Hardware» more  DATE 2002»
14 years 3 months ago
Library Compatible Ceff for Gate-Level Timing
Accurate gate-level static timing analysis in the presence of RC loads has become an important problem for modern deep-submicron designs. Non-capacitive loads are usually analyzed...
Bernard N. Sheehan
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
14 years 2 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
ASPDAC
2000
ACM
80views Hardware» more  ASPDAC 2000»
14 years 2 months ago
An interleaved dual-battery power supply for battery-operated electronics
 After a detailed analysis and discussion of two important characteristics of today’s battery cells (i.e., their current-capacity and current-voltage curves), this paper descr...
Qing Wu, Qinru Qiu, Massoud Pedram
ITC
1997
IEEE
107views Hardware» more  ITC 1997»
14 years 2 months ago
On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...
Benoît R. Veillette, Gordon W. Roberts
SIGMETRICS
1990
ACM
129views Hardware» more  SIGMETRICS 1990»
14 years 2 months ago
An Analytical Model of Multistage Interconnection Networks
Multiprocessors require an interconnection network to connect processors with memory modules. The performance of the interconnection network can have a large effect upon overall s...
Darryl L. Willick, Derek L. Eager