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» Formal analysis of hardware requirements
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DATE
2006
IEEE
91views Hardware» more  DATE 2006»
14 years 29 days ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
ASPDAC
2005
ACM
103views Hardware» more  ASPDAC 2005»
13 years 11 months ago
MAIA: a framework for networks on chip generation and verification
- The increasing complexity of SoCs makes networks on chip (NoC) a promising substitute for busses and dedicated wires interconnection schemes. However, new tools need to be develo...
Luciano Ost, Aline Mello, José Palma, Ferna...
MASCOTS
2007
13 years 10 months ago
A Turnover based Adaptive HELLO Protocol for Mobile Ad Hoc and Sensor Networks
—We present a turnover based adaptive HELLO protocol (TAP), which enables nodes in mobile networks to dynamically adjust their HELLO messages frequency depending on the current s...
François Ingelrest, Nathalie Mitton, David ...
OSDI
1994
ACM
13 years 10 months ago
The Design and Evaluation of a Shared Object System for Distributed Memory Machines
This paper describes the design and evaluation of SAM, a shared object system for distributed memory machines. SAM is a portable run-time system that provides a global name space ...
Daniel J. Scales, Monica S. Lam
HPCA
2011
IEEE
13 years 1 months ago
Checked Load: Architectural support for JavaScript type-checking on mobile processors
Dynamic languages such as Javascript are the de-facto standard for web applications. However, generating efficient code for dynamically-typed languages is a challenge, because it...
Owen Anderson, Emily Fortuna, Luis Ceze, Susan Egg...