38 search results - page 6 / 8 » Formal verification of LTL formulas for SystemC designs |
CHARME
2003
Springer
13 years 11 months ago
2003
Springer
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Model checking techniques have traditionally dealt with temporal logic languages and automata interpreted over -words, i.e., infinite in the future but finite in the past. However...
SIGSOFT
2005
ACM
14 years 8 months ago
2005
ACM
We present a technique that enables the use of finite model finding to check the satisfiability of certain formulas whose intended models are infinite. Such formulas arise when us...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Most hardware description languages do not enforce determinacy, meaning that they may yield races. Race conditions pose a problem for the implementation, verification, and validat...