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» Formal verification of analog designs using MetiTarski
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ICFEM
2009
Springer
13 years 5 months ago
Verifying Ptolemy II Discrete-Event Models Using Real-Time Maude
Abstract. This paper shows how Ptolemy II discrete-event (DE) models can be formally analyzed using Real-Time Maude. We formalize in Real-Time Maude the semantics of a subset of hi...
Kyungmin Bae, Peter Csaba Ölveczky, Thomas Hu...
ENTCS
2008
90views more  ENTCS 2008»
13 years 7 months ago
Formal Verification of Websites
In this paper, a model for websites is presented. The model is well-suited for the formal verification of dynamic as well as static properties of the system. A website is defined ...
Sonia Flores, Salvador Lucas, Alicia Villanueva
ASPDAC
2004
ACM
94views Hardware» more  ASPDAC 2004»
13 years 11 months ago
Improving simulation-based verification by means of formal methods
The design of complex systems is largely ruled by the time needed for verification. Even though formal methods can provide higher reliability, in practice often simulation based ve...
Görschwin Fey, Rolf Drechsler
DAC
2006
ACM
14 years 8 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu
DAC
2000
ACM
14 years 8 months ago
Formal verification of iterative algorithms in microprocessors
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
Mark Aagaard, Robert B. Jones, Roope Kaivola, Kath...