299 search results - page 16 / 60 » Formal verification of analog designs using MetiTarski |
JUCS
2010
13 years 2 months ago
2010
: This paper formalizes UML class diagrams and structural patterns as mathematical objects and provides a precise notion of conformance of a structural model specified as a class d...
IJCAI
2003
13 years 8 months ago
2003
This paper addresses the formal verification of diagnosis systems. We tackle the problem of diagnosability: given a partially observable dynamic system, and a diagnosis system obs...
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
13 years 11 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
JACM
2002
13 years 7 months ago
2002
We show how to use an interactive theorem prover, HOL, together with a model checker, SPIN, to prove key properties of distance vector routing protocols. We do three case studies: ...
CCS
2009
ACM
13 years 11 months ago
2009
ACM
We present an approach for the design and analysis of an electronic voting machine based on a novel combination of formal verification and systematic testing. The system was desig...