299 search results - page 7 / 60 » Formal verification of analog designs using MetiTarski |
FMCAD
2007
Springer
14 years 1 months ago
2007
Springer
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
PERCOM
2010
ACM
13 years 5 months ago
2010
ACM
In autonomic networks, the self-configuration of network entities is one of the most desirable properties. In this paper, we show how formal verification techniques can verify the ...
ICSE
2009
IEEE-ACM
13 years 5 months ago
2009
IEEE-ACM
This paper presents experiments realized by Airbus on model checking a safety critical system, lessons learnt and ways forward to extend the industrial use of formal verification ...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
Language containment is a method for design verification that involves checking if the behavior of the system to be verified is a subset of the behavior of the specifications (pro...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...