This paper addresses the need for formal specification and runtime verification of system-level requirements of distributed reactive systems. It describes a formalism for specifyi...
We formalize and study business process systems that are centered around "business artifacts", or simply "artifacts". This approach focuses on data records, kn...
Alin Deutsch, Richard Hull, Fabio Patrizi, Victor ...
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
End-to-end latency of messages is an important design parameter that needs to be within specified bounds for the correct functioning of distributed real-time control systems. In t...
Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. R...
The soundness of device drivers generally cannot be verified in isolation, but has to take into account the reactions of the hardware devices. In critical embedded systems, interf...