178 search results - page 21 / 36 » Formally Specifying and Verifying Real-Time Systems |
FDL
2007
IEEE
14 years 1 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
ISSS
2000
IEEE
13 years 12 months ago
2000
IEEE
The ever increasing complexity of embedded systems consisting of hardware and software components poses a challenge in verifying their correctness, New verification methods that o...
STTT
2008
13 years 7 months ago
2008
Abstract. Managing access control policies in modern computer systems can be challenging and error-prone. Combining multiple disparate access policies can introduce unintended cons...
ASE
2002
13 years 7 months ago
2002
This paper describes a specialized interface to PVS called TAME (Timed Automata Modeling Environment) which provides automated support for proving properties of I/O automata. A maj...
CSFW
2005
IEEE
14 years 1 months ago
2005
IEEE
Availability is a critical issue in modern distributed systems. While many techniques and protocols for preventing denial of service (DoS) attacks have been proposed and deployed ...