9110 search results - page 1675 / 1822 » Formally-Based Design Evaluation |
133
Voted
IPPS
2009
IEEE
15 years 10 months ago
2009
IEEE
The use of asymmetric multi-core processors with onchip computational accelerators is becoming common in a variety of environments ranging from scientific computing to enterprise...
142
click to vote
IPPS
2009
IEEE
15 years 10 months ago
2009
IEEE
In many scientific applications, significant time is spent tuning codes for a particular highperformance architecture. Tuning approaches range from the relatively nonintrusive (...
153
click to vote
ISCA
2009
IEEE
15 years 10 months ago
2009
IEEE
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
121
Voted
MICRO
2009
IEEE
15 years 10 months ago
2009
IEEE
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
145
click to vote
MICRO
2009
IEEE
15 years 10 months ago
2009
IEEE
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...