202 search results - page 19 / 41 » Framework for Fault Analysis and Test Generation in DRAMs |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
COMPSAC
2003
IEEE
14 years 21 days ago
2003
IEEE
Usual techniques for automatic test data generation are based on the assumption that a complete oracle will be available during the testing process. However, there are programs fo...
UML
2004
Springer
14 years 22 days ago
2004
Springer
We describe the tools and interfaces created by the AGEDIS project, a European Commission sponsored project for the creation of a methodology and tools for automated model driven ...
ATS
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
WEA
2005
Springer
14 years 26 days ago
2005
Springer
Abstract. A5/1 pseudo-random bit generator, known from GSM networks, potentially might be used for different purposes, such as secret hiding during cryptographic hardware testing, ...