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DAC
2003
ACM
14 years 9 months ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
DAC
2003
ACM
14 years 9 months ago
Accurate timing analysis by modeling caches, speculation and their interaction
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...
Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
DAC
2005
ACM
14 years 9 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
MICCAI
2006
Springer
14 years 9 months ago
Simulation of Acquisition Artefacts in MR Scans: Effects on Automatic Measures of Brain Atrophy
Automatic algorithms in conjunction with longitudinal MR brain images can be used to measure cerebral atrophy, which is particularly pronounced in several types of dementia. An atr...
Oscar Camara-Rey, Beatrix I. Sneller, Gerard R. Ri...
ICSE
2009
IEEE-ACM
14 years 9 months ago
Analyzing critical process models through behavior model synthesis
Process models capture tasks performed by agents together with their control flow. Building and analyzing such models is important but difficult in certain areas such as safety-cr...
Christophe Damas, Bernard Lambeau, Francois Roucou...