Accurate timing analysis by modeling caches, speculation and their interaction

Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysis, but also modeling the effects of complex microarchitectural features in modern processors. Speculative execution and caching are very common in current processors. Hence one needs to model the effects of these features on the Worst Case Execution Time (WCET) of a program. Even though the individual effects of these features have been studied recently, their combined effects have not been investigated. We do so in this paper. This is a non-trivial task because speculative execution can indirectly affect cache performance (e.g., speculatively executed blocks can cause additional cache misses). Our technique starts from the control flow graph of the embedded program, and uses integer linear programming to estimate the program's WCET. The accuracy of our modeling is illustrated by tight estimates obtained...

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
• Keywords: Case Execution Time, DAC 2003, Design Automation, Speculative Execution, Worst Case Execution