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ICCAD
1999
IEEE
77views Hardware» more  ICCAD 1999»
14 years 22 days ago
Symbolic functional and timing verification of transistor-level circuits
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...
Clayton B. McDonald, Randal E. Bryant
FMCAD
2007
Springer
14 years 2 months ago
Formal Verification of Partial Good Self-Test Fencing Structures
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
Adrian E. Seigler, Gary A. Van Huben, Hari Mony
TE
2010
104views more  TE 2010»
13 years 3 months ago
Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum
Abstract--As demand increases for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used i...
Scott C. Smith, Waleed Al-Assadi, Jia Di
DAC
1999
ACM
14 years 22 days ago
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits
High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs. The problem is that domino logic comes at a...
Priyadarshan Patra, Unni Narayanan
TSMC
2002
134views more  TSMC 2002»
13 years 8 months ago
Incorporating soft computing techniques into a probabilistic intrusion detection system
There are a lot of industrial applications that can be solved competitively by hard computing, while still requiring the tolerance for imprecision and uncertainty that can be explo...
Sung-Bae Cho