570 search results - page 85 / 114 » From Program Verification to Program Synthesis |
EMSOFT
2006
Springer
14 years 2 months ago
2006
Springer
We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has...
BCS
2008
14 years 3 days ago
2008
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
FOAL
2008
ACM
14 years 6 days ago
2008
ACM
Often, insertion of several aspects into one system is desired and in that case the problem of interference among the different aspects might arise, even if each aspect individual...
DAC
2003
ACM
14 years 11 months ago
2003
ACM
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
ISESE
2003
IEEE
14 years 3 months ago
2003
IEEE
The two most common strategies for verification and validation, inspection and testing, are in a controlled experiment evaluated in terms of their fault detection capabilities. Th...