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ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
13 years 11 months ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...
SEKE
2010
Springer
13 years 5 months ago
Specification patterns can be formal and still easy
Abstract--Property specification is still one of the most challenging tasks for transference of software verification technology like model checking. The use of patterns has been p...
Fernando Asteasuain, Víctor A. Braberman
ASM
2008
ASM
13 years 9 months ago
Using EventB to Create a Virtual Machine Instruction Set Architecture
A Virtual Machine (VM) is a program running on a conventional microprocessor that emulates the binary instruction set, registers, and memory space of an idealized computing machine...
Stephen Wright
SAC
2003
ACM
14 years 1 months ago
Eliciting Coordination Policies from Requirements
Software coordination models and languages describe how agents, resources and processes work together to implement a software system. One of their limitations is that they are use...
Henry Muccini, Fabio Mancinelli
IFM
2010
Springer
152views Formal Methods» more  IFM 2010»
13 years 5 months ago
Specification and Verification of Model Transformations Using UML-RSDS
In this paper we describe techniques for the specification and verification of model transformations using a combination of UML and formal methods. The use of UML 2 notations to s...
Kevin Lano, Shekoufeh Kolahdouz Rahimi