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DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
16 years 5 days ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
ITC
1998
IEEE
174views Hardware» more  ITC 1998»
15 years 10 months ago
High volume microprocessor test escapes, an analysis of defects our tests are missing
This paper explores defects found in a high volume microprocessor when shipping at a low defect level. A brief description of the manufacturing flow along with definition of DPM i...
Wayne M. Needham, Cheryl Prunty, Yeoh Eng Hong
LICS
2009
IEEE
16 years 14 days ago
Ludics with Repetitions (Exponentials, Interactive Types and Completeness)
Abstract. Ludics is peculiar in the panorama of game semantics: we first have the definition of interaction-composition and then we have semantical types, as a set of strategies ...
Michele Basaldella, Claudia Faggian
CASSIS
2005
Springer
15 years 11 months ago
Mobile Resource Guarantees and Policies
This paper introduces notions of resource policy for mobile code to be run on smart devices, to integrate with the proof-carrying code architecture of the Mobile Resource Guarantee...
David Aspinall, Kenneth MacKenzie
CSL
2005
Springer
15 years 11 months ago
Permutative Logic
Recent work establishes a direct link between the complexity of a linear logic proof in terms of the exchange rule and the topological complexity of its corresponding proof net, ex...
Jean-Marc Andreoli, Gabriele Pulcini, Paul Ruet