Sciweavers

165 search results - page 16 / 33
» From the bitstream to the netlist
Sort
View
DAC
1999
ACM
14 years 9 hour ago
A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs
In deep submicron technology, IR-drop and clock skew issues become more crucial to the functionality of chip. This paper presents a oorplan-based power and clock distribution meth...
Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung
TMI
2010
251views more  TMI 2010»
13 years 2 months ago
3-D Scalable Medical Image Compression With Optimized Volume of Interest Coding
We present a novel 3-D scalable compression method for medical images with optimized volume of interest (VOI) coding. The method is presented within the framework of interactive te...
Victor Sanchez, Rafeef Abugharbieh, Panos Nasiopou...
FPGA
2003
ACM
138views FPGA» more  FPGA 2003»
14 years 27 days ago
Automatic transistor and physical design of FPGA tiles from an architectural specification
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...
Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron E...
KES
2005
Springer
14 years 1 months ago
Fast Video Retrieval via the Statistics of Motion Within the Regions-of-Interest
Abstract. It is a very important issue to quickly retrieve semantic information from a vast multimedia database. In this paper, we propose a statistic-based algorithm to retrieve t...
Jing-Fung Chen, Hong-Yuan Mark Liao, Chia-Wen Lin
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
14 years 27 days ago
PipeRoute: a pipelining-aware router for FPGAs
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
Akshay Sharma, Carl Ebeling, Scott Hauck