The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxen...
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
We describe a highly accurate but e cient fault simulator for interconnect opens, based on characterizing the standard cell library with SPICE; using transistor charge equations f...
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...