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VTS
2003
IEEE
127views Hardware» more  VTS 2003»
14 years 2 months ago
Bist Reseeding with very few Seeds
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the LFSR before filling the scan chain. The number of determinist...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
DFT
2005
IEEE
102views VLSI» more  DFT 2005»
13 years 11 months ago
Using Statistical Transformations to Improve Compression for Linear Decompressors
Linear decompressors are the dominant methodology used in commercial test data compression tools. However, they are generally not able to exploit correlations in the test data, an...
Samuel I. Ward, Chris Schattauer, Nur A. Touba
ET
2002
85views more  ET 2002»
13 years 9 months ago
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
Mehrdad Nourani, Amir Attarha
ICES
2010
Springer
106views Hardware» more  ICES 2010»
13 years 7 months ago
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application
Abstract. In this paper it is demonstrated how two issues from the area of testing electronic components can be merged and solved by means of a genetic algorithm. The two issues ar...
Jaroslav Skarvada, Zdenek Kotásek, Josef St...
NOCS
2007
IEEE
14 years 3 months ago
Transaction-Based Communication-Centric Debug
Abstract— The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC...
Kees Goossens, Bart Vermeulen, Remco van Steeden, ...