123 search results - page 11 / 25 » Functional Test Generation for FSMs by Fault Extraction |
VLSID
1993
IEEE
13 years 11 months ago
1993
IEEE
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
ASPDAC
2004
ACM
14 years 28 days ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
VTS
2002
IEEE
14 years 12 days ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
VTS
2000
IEEE
13 years 12 months ago
2000
IEEE
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
DATE
2000
IEEE
13 years 12 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...