174 search results - page 10 / 35 » Functional Test Generation for Full Scan Circuits |
DAC
2004
ACM
14 years 2 months ago
2004
ACM
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
ET
1998
13 years 10 months ago
1998
This paper explores the design of efficient test sets and test-pattern generators for online BIST. The target applications are high-performance, scalable datapath circuits for whi...
VTS
2002
IEEE
14 years 3 months ago
2002
IEEE
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
DAC
1997
ACM
14 years 3 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
EH
2000
IEEE
14 years 3 months ago
2000
IEEE
How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digit...