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ICCD
2006
IEEE
133views Hardware» more  ICCD 2006»
14 years 5 months ago
Patching Processor Design Errors
— Microprocessors can have design errors that escape the test and validation process. The cost to rectify these errors after shipping the processors can be very expensive as it m...
Satish Narayanasamy, Bruce Carneal, Brad Calder
IPPS
2009
IEEE
14 years 3 months ago
Exploring FPGAs for accelerating the phylogenetic likelihood function
Driven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion over the last 2-3 years. The growth of biological seq...
Nikolaos Alachiotis, Euripides Sotiriades, Apostol...
ICSE
2007
IEEE-ACM
14 years 9 months ago
A Data Model to Support End User Software Engineering
Many end user programming tools such as spreadsheets and databases offer poor support for representing a level of abstraction that is intuitive to users. For example, users must w...
Christopher Scaffidi
SEUS
2007
IEEE
14 years 3 months ago
A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture
In this paper we present a distributed Hardware-in-the-Loop (HiL) simulation approach that supports the verification and validation activities in an integrated architecture as rec...
Martin Schlager, Roman Obermaisser, Wilfried Elmen...
JUCS
2007
208views more  JUCS 2007»
13 years 8 months ago
The Architecture and Circuital Implementation Scheme of a New Cell Neural Network for Analog Signal Processing
: It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network ...
Youren Wang, Zhiqiang Zhang, Jiang Cui