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» Functional Validation of Programmable Architectures
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WSC
2008
13 years 11 months ago
Architecture for modeling, simulation, and execution of PLC based manufacturing system
In this paper, we propose an integrated architecture for modeling, simulation, and execution of PLC (Programmable Logic Controller) based manufacturing system. The main objective ...
Devinder Thapa, Chang Mok Park, Kwan Hee Han, Sang...
ICIP
1999
IEEE
14 years 10 months ago
Architecture of Embedded Video Processing in a Multimedia Chip-Set
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
Egbert G. T. Jaspers, Peter H. N. de With
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
14 years 11 days ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
14 years 2 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
CORR
2002
Springer
100views Education» more  CORR 2002»
13 years 8 months ago
A neural model for multi-expert architectures
We present a generalization of conventional artificial neural networks that allows for a functional equivalence to multi-expert systems. The new model provides an architectural fr...
Marc Toussaint